The total-fee FP64-matrix bet that powered Frontier hasn’t been killed, but it is not carrying the burden. It originated on RDNA gaming GPUs to compensate for slim GDDR buses; AMD reused the IP for AI on CDNA 3, the place attention KV reuse and weight reuse match a large LLC unusually properly. The platform conforms to OCP’s UBB 2.0: the identical mechanical socket as an NVIDIA HGX baseboard, so server distributors can ship AMD or NVIDIA on the same chassis without redesigning the system. The fancier optimization work only issues once all of the gates are open. The form factor is Open Rack Wide (ORW) (Meta’s 2025 OCP submission, double-broad and liquid-cooled), not an AMD-proprietary chassis. For inference workloads by way of 2024-2025, AMD’s scale-up did not need to match NVL72 at the rack to be aggressive on the field. CDNA 2’s MI250X was AMD’s first multi-chip GPU: two Aldebaran GCDs side-by-side on a 2.5D EFB natural substrate, joined by four in-package deal Infinity Fabric hyperlinks at 400 GB/s aggregate, but introduced to software as two separate GPUs. Where NVIDIA’s architectural ambition lives inside each SM (new tensor primitives, new async machinery, new operand stores each technology), AMD’s lives between the CUs, in how a lot of them could be bonded right into a single coherent package deal.
AMD’s Matrix Core stayed put. NVIDIA stayed monolithic by means of H100 and solely went to two reticle-limit dies on B200 by way of 2.5D CoWoS-L. The format that ships in MI355X is equivalent to what ships in B200 and TPU v8. The form hasn’t meaningfully changed since GCN in 2012; what scales is the count (one hundred twenty CUs on MI100, 220 on MI250X, 304 on MI300X, 256 on MI355X) and the packaging that bonds them. MI300X served coaching, HPC, and inference together; MI355X is an AI chip first. This was the hole that mattered for training, and the gap that Helios is constructed to shut. Helios is AMD’s first rack-scale scale-up area, delivery in 2H 2026 alongside MI455X. Through MI355X, AMD’s scale-up means an 8-GPU OAM platform over Infinity Fabric. AMD’s memory hierarchy has fewer general-function tiers than NVIDIA’s, with one large cache that NVIDIA does not have in any respect. Off-chip, the HBM capacity grows aggressively: 32 → sixty four → 128 → 192 → 256 → 288 GB across MI100 / MI210 / MI250X / MI300X / MI325X / MI350X, matching or exceeding the contemporary NVIDIA flagship in each technology from 2021 onward. Customers running larger fashions on MI300X clusters scaled across multiple 8-GPU packing containers by way of Ethernet, paying scale-out latency for what NVIDIA users may keep inside scale-up.
31 TB HBM4, 1.Four PB/s aggregate HBM bandwidth, 2.9 ExaFLOPS FP4 / 1.4 ExaFLOPS FP8, 260 TB/s of scale-up bandwidth, forty three TB/s of scale-out. Replace 2 of the eight XCDs with three Zen 4 CCDs, depart HBM and Infinity Cache and the IODs intact, and let CPU and GPU share one bodily tackle house backed by HBM3 with hardware coherence. The memory bet has a scaling consequence: when 8 MI300X chips hold 1.5 TB of HBM and 8 MI350X chips hold 2.3 TB, you may match a 405B-parameter mannequin in FP8 inside a single 8-GPU field (weights, KV cache, and headroom for longer contexts and larger batches), where the identical model on 8× H100 (640 GB) requires cautious sharding. 1,075 GB/s per GPU) but retains the 8-GPU shape. Each MI300X has 7 IF hyperlinks (one to each peer in the field) at 128 GB/s bidirectional, giving 896 GB/s of per-GPU mesh bandwidth in a fully-related all-to-all topology. Even a type of particulars is usually enough to flip a page from “training knowledge summary” to “cited reference”.
Chunking content into tiny sections or rewriting each heading as a query is pointless, as a result of models learn context across the entire page. Google’s information tells creators to concentrate on “unique, invaluable, people-first content” moderately than commodity content that re-states what each other page on the subject already says (supply). The deeper model of this recommendation lives in Google’s useful content material steerage, which goes into how one can demonstrate firsthand experience, actual experience, and original perspective. The snippet directives above are documented in Google’s meta tags reference. HPC and AI are the same bet till they don’t seem to be: ship full-charge FP64 matrix from CDNA 2 by way of CDNA 3, then bifurcate at CDNA four once inference economics decisively favour low precision. CDNA 2 doubled the FP64 path to a full-rate matrix at 256 FLOPs/CU/cycle: uniquely AMD, the bet that put MI250X into Frontier. The CDNA four inflection deserves its own line: per-CU FP64 throughput halved. The throughput numbers inform the format story immediately. The numbers rating algorithms take a look at are the 28-day field knowledge from actual Chrome customers (CrUX), not a Lighthouse run in your laptop computer.